1. Technical Field
Electronic storage arrays having storage or memory cells formed on integrated circuit chips are well known in the art. A variety of trade-offs must be considered in selecting a particular design for a given application. For example, advantageous features such as high speed and DC stability usually require greater power consumption and a greater area per cell on the integrated circuit chip.
Accordingly, it is a primary object of the present invention to enable a very high density, DC stable memory cell and, in its most preferred embodiment, to include only a single field effect transistor device in such cell to make it compact.
2. Background Information
A variety of approaches have been taken to eliminating the need for refresh circuitry which is necessary in so called dynamic memory cells, thereby to achieve static or DC capability. In order to provide background material so as to enable a full appreciation of the present invention, reference may be made to U.S. Pat. No. 4,142,111 which describes a one-transistor, fully static semiconductor memory cell involving a conventional MOS transistor, along with a field implanted resistance and a vertical P-channel junction type field effect transistor.
Another U.S. patent of interest is No. 3,914,749 of the present applicant, and assigned to the assignee of the present invention. This patent describes a single device DC-stable memory cell comprising a bistable bipolar transistor having a lightly doped base and an emitter which is substantially coextensive with the base.
Other background material is as follows:
U.S. Pat. No. 3,725,881 PA1 U.S. Pat. No. 4,070,653 PA1 U.S. Pat. No. 4,092,735 PA1 U.S. Pat. No. 4,142,112.
Baliga, "An Improved GAMBIT Device Structure", IEEE Transactions on Electron Devices, volume ED-25, number 12, December 1978, pages 1411-12. Thomas, "The NEGIT: A Surface-Control Negative Impedance Transistor", IEEE Transactions on Electron Devices, volume ED-24, number 8, August 1977, pages 1070-1076.
The present invention is also related to an invention of applicant entitled "Electronic Storage Array Having DC Stable Conductivity Modulated Storage Cells" filed Dec. 28, 1979 Ser. No. 107,812, assigned to the assignee of the present invention. The invention of this related application includes an electronic storage array with DC stage cells. However, such cells relay on the principle of conductivity modulation in a region adjacent the base region of a transistor device.
Whatever the merits of the cited references, they do not disclose the principle of the present invention which relies on the aforenoted channel pinch-off effect by a controlled electrode, such electrode being controlled by the "write" pulse input to the memory cell; the pinch-off effect acting to establish the cell in one of two stable states.